Digital data transfer generally involves the operations of data transmission by a master device on a data bus and reception of the data by a slave device. In most bus systems, timing characteristics of the data transmissions are determined all or in part by the master device. In these systems the slave device must synchronize with the master device through a clock signal that is either transmitted by or derived from the master device.
Data bus transfers are performed synchronously with a bus clock to determine the timing between control signal edge transitions, or asynchronously with the data access timing determined by the slave device. Synchronous data transfers have a predetermined time within which both address decode and data access must be performed by the slave device. Asynchronous data transfers allow the slave device to determine the time required for data access operations but require a predetermined time period during which the slave device must perform the address decode function.
In computer networks having more than one master device connected to the data bus, a method of bus arbitration is necessary. In synchronous bus arbitration systems, a bus clock may be used along with vie logic techniques. This method of bus arbitration requires a clock frequency selected to match both the speed of the bus master devices and the length of the bus. In typical asynchronous bus arbitration systems, the timing between arbitration states is fixed, and the priority of bus acquisition may be determined by a daisy chained bus grant signal. However, daisy chained arbitration does not continue to function correctly when a master device is removed from the system because removal of a master interrupts the daisy chained circuit.
In computer networks that rely on clock signals for bus arbitration and data transfer, the clock timing must be set to handle worst case conditions attributable to system technology, environmental conditions such as temperature, and the physical separation of master and slave devices. Setting the timing in these systems penalizes most operations which do not exhibit worst case conditions. Adjusting the timing parameters to fit each operation removes this penalty but causes incompatabilities because components designed for one operation may not perform correctly in another.
When the relative distance between the master and slave devices or the data transmission rate is increased, the propagation delay of the signal becomes a significant portion of the data transfer period. In a typical system, a master device has no knowledge of what the relative signal skew time will be between it and the slave devices. Thus, bus timing specifications are forced to be set for operation under worst case bus length, temperature, and device speed conditions.
In VLSI systems, signal propagation delay becomes of significant importance. The data transmission rates in VLSI systems are so high that a propagation delay of a few nanoseconds can be a significant factor in determining data transmission timing. Because VLSI devices using conventional bus technology must be designed to operate under worst case signal propagation conditions, a master VLSI device must use transfer timing that will allow a slave device to be placed on another circuit board (50 to 100 nanoseconds propagation delay) even though the slave device may be placed within the same package (1 to 5 nanoseconds propagation delay).
The basic problem of digital data transmission is that all slave devices do not see the transmission clock signal at the same time, and as the speed or distance of data transmission increases, so does the relative clock skew between devices. Therefore, large computer networks or VLSI systems cannot operate at their full performance potential without a self-timed data transfer technique that does not rely on a system clock signal. Thus, there is a need for a self-timed bus arbitration and data transfer scheme that allows computer systems to operate at their optimum efficiency of all times rather than under constant worst case constraints.